[bootlin/training-materials updates] master: Consistent naming of the RISC-V architecture (50ae6fa0)

Michael Opdenacker michael.opdenacker at bootlin.com
Mon Mar 8 10:18:14 CET 2021

Repository : https://github.com/bootlin/training-materials
On branch  : master
Link       : https://github.com/bootlin/training-materials/commit/50ae6fa02fe4f018d3e1cc23bb04a20fa124cba3


commit 50ae6fa02fe4f018d3e1cc23bb04a20fa124cba3
Author: Michael Opdenacker <michael.opdenacker at bootlin.com>
Date:   Mon Mar 8 10:18:14 2021 +0100

    Consistent naming of the RISC-V architecture
    Signed-off-by: Michael Opdenacker <michael.opdenacker at bootlin.com>


 slides/sysdev-embedded-linux/sysdev-embedded-linux.tex | 2 +-
 slides/sysdev-intro/sysdev-intro.tex                   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex b/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex
index a3907798..3ba37faf 100644
--- a/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex
+++ b/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex
@@ -1424,7 +1424,7 @@ $(eval $(autotools-package))
     \item But probably too costly to maintain
           and unnecessarily big for production systems.
     \item Available on multiple architectures: ARM (\code{armel},
-          \code{armhf}, \code{arm64}), MIPS, PowerPC, RiscV (in progress)...
+          \code{armhf}, \code{arm64}), MIPS, PowerPC, RISC-V (in progress)...
     \item Software is compiled natively by default.
     \item Use the \code{debootstrap} command to build a root
           filesystem for your architecture, with a custom selection
diff --git a/slides/sysdev-intro/sysdev-intro.tex b/slides/sysdev-intro/sysdev-intro.tex
index ba22d9f1..d7bbd39c 100644
--- a/slides/sysdev-intro/sysdev-intro.tex
+++ b/slides/sysdev-intro/sysdev-intro.tex
@@ -233,7 +233,7 @@
     (multimedia, industrial)
   \item ARM, with hundreds of different {\em System on Chip}s ({\em
 	SoC}: CPU + on-chip devices, for all sorts of products)
-  \item RiscV, the rising architecture with a free instruction set
+  \item RISC-V, the rising architecture with a free instruction set
         (from high-end cloud computing to the smallest embedded systems)
   \item PowerPC (mainly real-time, industrial applications)
   \item MIPS (mainly networking applications)

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